The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a cylinder type capacitor.
A memory cell size has continuously decreased as the design rule of dynamic random access memories (DRAM) also decreases. Accordingly, the height of a capacitor has continuously increased and the thickness has become smaller in order to maintain a desired charge capacitance. The height has increased and the thickness has decreased because the charge capacitance is proportionate to the surface area of an electrode and the dielectric constant of a dielectric layer, and is inversely proportionate to the distance between the electrodes, i.e., the thickness of the dielectric layer.
FIGS. 1A and 1B illustrate cross-sectional views of a conventional method for fabricating a capacitor. A line A-A′ represents a cross-sectional view of a substrate structure having a zigzag arrangement with a small spacing distance. A line B-B′ represents a cross-sectional view of the substrate structure having a zigzag arrangement with a large spacing distance.
Referring to FIG. 1A, an insulation layer 12 is formed over a semi-finished substrate 11. Stack structures, including storage node contact plugs 13 and barrier metals 14, are formed in the insulation layer 12. An etch stop layer and a sacrificial layer are formed over the insulation layer 12 including the stack structures. The sacrificial layer and the etch stop layer are etched to form a patterned sacrificial layer 16 and a patterned etch stop layer 15 thereby defining open regions. Cylinder type storage nodes 17 are then formed on the surface of the open regions. The open regions have a certain aspect ratio. The aspect ratio is a ratio of a bottom critical dimension ‘W’ to a height ‘H’ of the open regions.
Referring to FIG. 1B, a wet dip out process is performed to remove the patterned sacrificial layer 16. Thus, inner walls and outer walls of the cylinder type storage nodes 17 are exposed. However, as the design rule continuously decreases, a distance between cylinder type storage nodes has also decreased in the cylinder type capacitor formation process. Thus, generation of bridges between neighboring storage nodes is increased despite the optimization of the wet dip out process.
FIG. 1C illustrates a graph showing the probability of bridge generation according to different aspect ratios of storage nodes. For instance, when a ratio between the bottom critical dimension ‘W’ to the height ‘H’ of the storage nodes in FIG. 1A is larger than 12, the storage nodes may lean and cause neighboring storage nodes to stick together, thereby generating bridges.
FIG. 1D illustrates a micrographic view of storage nodes without bridge generation. FIG. 1E illustrates a micrographic view of storage nodes with bridge generation. In FIG. 1D, an aspect ratio is 12, and the storage nodes are arranged with a uniform spacing distance. In FIG. 1E, an aspect ratio is 17, and the storage nodes lean and stick together.
The value of the aspect ratio causing the leaning may be variable according to the property or thickness of the electrode and according to dry conditions of the sacrificial layer after performing a wet etching for forming the cylinders. The undesirable results shown in FIG. 1E generally occur when the aspect ratio is larger than 14 for a titanium nitride (TiN) electrode.
The leaning may be caused by the surface tension of water existing between the storage nodes during a dry process which is performed after the wet dip output process. As the DRAM becomes smaller, the height of the capacitor may need to be increased accordingly to maintain the surface area of the capacitor. However, the height of the capacitor generally needs to be decreased in order to keep the aspect ratio below a certain level and reduce the bottom critical dimension increase. Thus, it may be difficult to maintain a sufficient surface area. Accordingly, an effective thickness of the dielectric layer may need to be reduced in order to maintain a satisfactory capacitance because of an insufficient capacitor surface area.